Phase locked loops (“PLL”) have been used extensively in analog electrical systems and communication systems. In today's high performance systems operating within increasingly stringent timing constraints, PLLs are being introduced in more general digital electronic circuits. For example, Application Specific Integrated Circuits (ASICs) used in a variety of circuit applications typically include on-chip PLLs for clock signal distribution.
The key advantages that PLLs bring to clock distribution are phase/delay compensation, frequency multiplication and duty cycle correction. A PLL enables one periodic signal or clock to be phase-aligned to frequency multiples of a reference clock. As the name implies, the output of the PLL locks onto the incoming reference clock signal and generates a periodic output signal with a frequency equal to the average frequency of the reference clock. When the output PLL signal tracks the reference signal, the PLL is said to be “locked.”
A PLL, however, will only remain locked over a limited frequency range or shift in frequency called a hold-in or lock range. The PLL generally tracks the reference signal over the lock range, provided the reference frequency changes slowly. This maximum “locked sweep rate” is the maximum rate of change of the reference frequency for which the PLL will remain locked. If the frequency changes faster than this rate, the PLL will drop out of lock.
Other factors may cause loss of lock that may occur unexpectedly and suddenly. For example, Single Event Transients (SETs) caused by particle radiation (not uncommon in aerospace applications) may disrupt the PLL circuit and cause loss of lock. Integrated circuits used in space, weapons, or aviation applications are more likely to be exposed to such charged particle radiation. Particle-induced circuit disturbances are random and are commonly referred to as Single Event Effects (SEEs). SEEs can take on many forms. If the particle strike results in a bit flip or other form of corruption of stored data, this is known as a Single Event Upset (SEU), or a soft error. If the particle causes a transient voltage disturbance on a node of a logic circuit, this is known as an SET. If the node is in a clock network, a temporary voltage disturbance on a circuit node can generate a false clock pulse in a portion of the system. If undetected, loss of lock may disrupt and interfere with circuit operation.
To detect a loss of lock, lock detectors are utilized. Lock detectors typically monitor the reference clock and the PLL output signal. The frequencies of these two signals are compared. If the frequencies match, the PLL is determined to be locked. Unfortunately, even though a lock detector may flag an error event, some of the components of a PLL may still be affected adversely when a PLL falls out of lock. One component that may be affected is the voltage controlled oscillator (VCO). A VCO is used to create a PLL output signal with a periodic waveform. As the name implies, a VCO outputs a signal with a frequency indicative of an input voltage signal.
When a lock condition in the PLL is lost, the VCO may continue to output a signal. Under normal operation, this signal is used to create a feedback signal that is used to determine the amount of voltage that should be applied to the VCO in order to maintain a desired output. However, when a PLL loses lock, this feedback signal may deviate from normal operation. Using the feedback signal for feedback, the VCO may also increase or decrease to the point that it is out of a normal operating range. If this occurs, circuits that rely on the PLL may be adversely affected.
One example of a VCO deviating out of normal operation may occur when a SEE causes a capacitor within a charge pump to discharge. Discharging the capacitor may cause a significant deviation in a PLL output signal. Correspondingly, a loss of lock may be flagged. Despite the flagged loss of lock, the VCO may continue to produce a signal having a waveform that is increasing in frequency. Eventually circuits that employ the PLL, such as an ASIC, as well as the PLL will need to be globally reset in order to return to a normal operating condition.
In some circumstances, however, a PLL may recover without having to reset the PLL or circuits that depend on the PLL. Some SET events may cause a disruption for only one cycle of the PLL. This may not be significant enough to cause a VCO to deviate into an undesirable operating range. The VCO may recover naturally in a short amount of time. Thus, there is a need for a circuit that appropriately resets a phase locked loop, or VCO, after lock has been lost for a predetermined amount of time.